Generally, through substrate vias (TSVs) are formed in a semiconductor wafer by initially forming an opening at least partially through a substrate. A barrier layer is formed to line the opening in order to prevent a later-formed conductive material (e.g., copper) from diffusing into the substrate, where it might deteriorate the overall performance of other devices formed on the semiconductor wafer. As such, this barrier layer prevents damage caused by the conductive material. Once the conductive material has been formed, a second barrier layer may be formed on top of TSV to prevent diffusion of the conductive material that connects to top of TSV, and a third barrier layer may be formed on the bottom of the TSV to prevent diffusion of the conductive material that connects to top of TSV.
However, the processes and materials utilized to form these barrier layers are not ideal for the different and divergent locations where barrier layers may be desired. For example, a process such as physical vapor deposition (PVD) may form a material that has a suitable resistance on the top of the TSV and on the bottom of the TSV. However, such a PVD process does not provide an adequate coverage of the sidewalls (also known as the step coverage of the sidewalls) in high aspect ratio openings such as those utilized for the formation of TSVs. As such, a material formed from a PVD process is not suitable for lining a TSV.
Another process, such as chemical vapor deposition (CVD), may be able to achieve a suitable step coverage along the sidewalls of the TSV in order to prevent conductive material from diffusing out of the TSV. However, CVD also forms a material with a higher resistance than PVD. As such, in order to obtain this step coverage that CVD provides, the higher resistance of a material formed by CVD is also obtained. This tradeoff between step coverage and resistance makes barrier layers formed with CVD less than ideal for the top and bottom of the TSV.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.